Computer Systems: A Programmer's Perspective (Global Edition): Hardware Trade-offs: SRAM vs. DRAM Architecture

The Foundation of Hierarchy

The memory hierarchy relies on the trade-off between Static RAM (SRAM) and Dynamic RAM (DRAM). SRAM uses a 6-transistor bistable memory cell. Imagine an inverted pendulum: it is stable in two positions but metastable in the middle. This bistability makes it fast, expensive, and insensitive to disturbances. DRAM, conversely, stores bits as charge in a tiny capacitor (approx. 30 × 10⁻¹⁵ farads). Because charge leaks, DRAM is slower and requires constant refreshing.

DRAM Organization & Bus Transactions

To minimize pin count, DRAM bits are partitioned into $d$ supercells in a $r \times c$ grid where $rc=d$. Accessing data requires a two-step process: the Memory Controller sends a RAS (Row Access Strobe), moving a row to the row buffer, followed by a CAS (Column Access Strobe). This explains why sumarraycols is inherently slower: it misses the row buffer repeatedly.

Data Movement

Data travels via Bus transactions across the System Bus and Memory Bus, bridged by the I/O bridge. A movq A, %rax instruction (Read Transaction) triggers the bridge to translate the CPU's request into the DRAM's grid signals.

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QUESTION 1

Which physical characteristic explains why SRAM is faster but less dense than DRAM?

SRAM uses capacitors that require periodic refreshing.

SRAM uses a 6-transistor bistable cell, while DRAM uses a single transistor and capacitor.

DRAM uses the inverted pendulum principle for stability.

SRAM requires RAS/CAS strobing for every bit access.

QUESTION 2

In a 128 x 8 DRAM, why does the controller send the Row Address (RAS) and Column Address (CAS) separately?

To increase the power consumption defined by P = fCV².

To allow the CPU to perform polynomial evaluation in between.

To reduce the number of address pins required on the chip by minimizing max(br, bc).

To ensure the firmware can intercept the memory bus transaction.

QUESTION 3

Identify the sequence for a 'Read transaction' of 'movq A, %rax'.

CPU places address on System Bus -> I/O Bridge translates to Memory Bus -> DRAM returns data to CPU.

DRAM sends data to System Bus -> I/O Bridge sends to Register file.

CPU places data on Memory Bus -> Bridge translates to System Bus -> Address A is updated.

QUESTION 4

Match the address partitioning component: CI

The cache block offset

The cache set index

The cache tag

The DRAM supercell width

QUESTION 5

What would the hit rate be if the cache were twice as big for a grid array scan problem with a 64 B block size?

It would double exactly.

It depends on spatial locality; for a stride-1 scan, it remains (BlockSize - sizeof(type)) / BlockSize.

It would become 100% because of compulsory misses.

It would decrease because of conflict misses.

DRAM Dimension Optimization & Stride Analysis

Physical Layout vs. Algorithmic Access

Consider a system using a 512 x 4 DRAM module. The physical organization requires minimizing the pin count while the software executes a matrix transpose.

Determine the power-of-2 array dimensions (r, c) that minimize max(br, bc) for a 512 x 4 DRAM.

Solution:
For a 512 x 4 DRAM, the total number of supercells is d = 512. To minimize max(br, bc), the grid should be as close to square as possible. Since 512 is not a perfect square, we look for powers of 2. $2^9$ = 512. We can use r = 32 ($2^5$) and c = 16 ($2^4$), or vice-versa. Here, br = 5 and bc = 4. Thus, max(br, bc) = 5. The dimensions are 32 x 16.

How does the DRAM row-buffer (RAS/CAS) mechanism impact the performance of 'dst[j*dim + i] = src[i*dim + j]' when 'dim' is a large power of 2?

Solution:
When 'dim' is a large power of 2, 'src' is accessed in row-major (good spatial locality, row-buffer hits), but 'dst' is accessed in column-major (stride-N). This causes a 'RAS' request for every single write, as each 'dst' access likely maps to a different DRAM row, forcing the memory controller to constantly close and open rows (thrashing the row buffer).